1 fn6072.9 ISL45042 lcd module calibrator the v com voltage of an lcd panel needs to be adjusted to remove flicker. the ISL45042 can be used to digitally adjust a panel?s v com voltage by controlling its output sink current. the output of the ISL45042 is connected to an external voltage divider and an external v com buffer amplifier. in this application, the user can control the v com voltage with 7-bit accuracy (128 steps). once the desired v com setting is obtained, the settings can be stored in the non-volatile eeprom memory, which would then be automatically recalled during every power-up. the v com adjustment and non-volatile memory programming is through a single interface pin (ctl). once the desired programmed value is obtained, the counter enable pin (ce) can be used to prevent further adjustment or programming. the full-scale sink current of the ISL45042 is set using an external resistor connected to the set pin. the full-scale sink current determines the lowe st voltage of the external voltage divider. the ISL45042 is available in an 8 ld 3mmx3mm tdfn package with a maximum thickness of 0.8mm for ultra thin lcd panel design. pinout ISL45042 (8 ld tdfn) top view features ? 128-step adjustable sink current output ? 2.6v to 3.6v digital supply voltage operating range (3.0v minimum programming voltage) ? 4.5v to 20v analog supply voltage operating range (10.8v minimum programming voltage) ? rewritable eeprom for storing the optimum v com value ? output adjustment enable/disable control ? output guaranteed monotonic over-temperature ? two pin adjustment, programming and enable ? ultra thin 8 ld 3mmx3mm dfn (0.8mm max) ? pb-free (rohs compliant) applications ? lcd panels out avdd dnc gnd 1 2 3 4 8 7 6 5 set ce ctl v dd ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL45042irz 042z -40 to +85 8 ld 3x3 tdfn l8.3x3a notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic pa ckaged products employ special pb- free material sets, molding com pounds/die attach materials, and 100% matte tin plate plus anneal ( e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-f ree products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (m sl), please see device information page for ISL45042 . for more information on msl please see techbrief tb363 . data sheet caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. copyright ? intersil americas inc. 2005-2008, 2011. all rights reserved. all other trademarks mentioned are the property of their respective owners. april 13, 2011
2 fn6072.9 april 13, 2011 pin descriptions pin function out adjustable sink current output pin. th e current sinks into the out pin is equal to the dac setting times the maximum adjusta ble sink current divided by 128. see set pin function in ?pin descripti ons? on page 2 for the maximum adjustable sink current setting. avdd high-voltage analog supply. connects to top of external resistor divider to determine the v com voltage. 10.8v to 20v for eeprom programming, 4.5v to 20v normal operation (before/after pr ogramming). bypass to gnd with 0.1f de-coupling capacitor. dnc do not connect. this pin may be left unconnected or tied to gnd. do not apply any non-zero vo ltages or signals to this pin. gnd ground connection. v dd low-voltage digital supply for digital logic. typically 3v to 3.6v. bypass to gnd with 0.1f de-coupling capacitor. ctl internal counter up/down control and internal eeprom programming control input. if ce is high, a mid-to-low transition incre ments the 7-bit counter, raising the dac setting, increasing the out si nk current, and lowering the divider voltage at out. a mid-to- high transition decrements the 7-bit counter, lowering the dac setti ng, decreasing the out sink current, and increasing the divider voltage at out. applying 4.9v and above with appr opriately arranged timing will overwrite eeprom with the contents in the 7-bit counter . see eeprom programming section in ?electrical specifications? table on page 4 for details. ce counter enable pin with internal pull-down resistor. connect ce to vdd to enable adjustment of the output sink current. float or connect ce to gnd to prevent fu rther adjustment or programming. set maximum sink current adjustment point. co nnect a resistor from the set pin to gnd to set the maximum adjustable sink current of the out pin. the maximum adjus table sink current is equal to (avdd/20) divided by rset. block diagram ISL45042 digital interface with threshold sensors up/down counter with preset latches eeprom or nvl memory analog dcp and current output block avdd iout set ctl ce vdd gnd up dwn pwrup prgm por por prgm ibias read prgm memory 400k to 5m ISL45042
3 fn6072.9 april 13, 2011 absolute maximum rati ngs thermal information v dd to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+4v input voltages to gnd set, ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +4v avdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v ctl. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +17v output voltages to gnd out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +20v esd rating human body model device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75kv ctl to gnd (no eeprom content disruption). . . . . . . . . .7kv operating conditions temperature range ISL45042ir . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, notes 4, 5) ja (c/w) jc (c/w) 8 ld tdfn package. . . . . . . . . . . . . . . 47 12 moisture sensitivity (see technical brief tb363) all packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . level 1 maximum junction temperature (plastic package) . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp erase/write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10,000 data retention. . . . . . . . . . . . . . . . . . . . . . . . . . . 10 years @ +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. note: 4. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications test conditions: v dd = 3v, av dd = 18v, r set = 5k ? , r1 = 10k ? , r2 = 10k ? ; unless otherwise specified. typicals are at t a = +25c parameter symbol test conditions temp (c) min (note 13) typ max (note 13) units dc characteristics v dd supply range v dd range allowing programming 0 to 85 3 - 3.6 v operation without programming full 2.6 - 3.6 v v dd supply current i dd ce = v dd (note 10) full - - 65 a ce = gnd full - - 65 a avdd supply range avdd range allowing programming full 10.8 - 20 v operation without programming full 4.5 20 v av dd supply current (note 7) i avdd full 38 a ctl high voltage ctl ih 2.6v < v dd < 3.6v full 0.7*v dd -0.8*v dd v ctl low voltage ctl il 2.6v < v dd < 3.6v full 0.2*v dd -0.3*v dd v ctl high rejected pulse width ctl ihrpw full 20 - - s ctl low rejected pulse width ctl ilrpw full 20 - - s ctl high minimum pulse width ctl ihmpw full - - 200 s ctl low minimum pulse width ctl ilmpw full - - 200 s ctl minimum time between counts ctl mtc full - - 10 s ctl input current ictl ctl = gnd full - - 10 a ctl = v dd full - - 10 a ctl input capacitance ctl cap (note 9) full - 10 - pf ce input low voltage ce il 2.6v < v dd < 3.6v full - - 0.4 v ce input high voltage ce ih 2.6v < v dd < 3.6v full 0.7*v dd -- v ce minimum start-up time ce st (note 9) full - 1 - ms ISL45042
4 fn6072.9 april 13, 2011 ctl eeprom program voltage ctl prom 2.6v < v dd < 3.6v, (note 6) full 4.9 - 15.75 v ctl eeprom programming signal time ctl pt >4.9v full 200 - - s programming time p t full - - 100 ms set voltage resolution set vr (note 8) full 7 7 7 bits set differential nonlinearity set dn monotonic over-temperature full - - 1 lsb set zero-scale error set zse full - - 3 lsb set full-scale error set fse full - - 8 lsb set current iset through r set (note 11) full - 20 - a set external resistance set er to gnd, avdd = 20v full 10 - 200 k to gnd, avdd = 4.5v full 2.25 - 45 k to gnd, av dd = 15v, v dd = 3v v out > 2.5v (note 12) full 1 - 200 k avdd to set voltage attenuation avdd to set full - 1:20 - v/v out settling time out st to 0.5 lsb error band (note 9) full - 20 - s out voltage range v out full vset + 0.5v - 13 v out voltage drift out vd 25c < t a < 55c (note 9) 25 to 55 - <10 - mv notes: 6. ctl signal only needs to be greater than 4.9v to program eeprom. 7. tested at av dd = 20v. 8. the counter value is set to mid-scale 4 lsb?s in the production. 9. simulated and determined via design and not directly tested. 10. simulated maximum current draw when programming eeprom is 23ma; should be consider ed when designing power supply. 11. a typical current of 20a is calculated using av dd = 10v and r set = 24.9k . reference ?rset resistor? on page 6. 12. minimum value of r set resistor guaranteed when: av dd = 15v, v dd = 3.0v and when voltage on the vout pin is greater than 2.5v. reference equation 2 on page 6 with setting = 128. 13. compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. electrical specifications test conditions: v dd = 3v, av dd = 18v, r set = 5k ? , r1 = 10k ? , r2 = 10k ? ; unless otherwise specified. typicals are at t a = +25c (continued) parameter symbol test conditions temp (c) min (note 13) typ max (note 13) units ISL45042
5 fn6072.9 april 13, 2011 application information the application circuit to adjust the v com voltage in an lcd panel is shown in figure 1. the ISL45042 has a 128-step sink current resolution. the output is connected to an external voltage divider that decreases the output v com voltage as you increase the ISL45042 sink current. ctl pin the adjustment of the output v com voltage and the programming of the non-volatile memory are provided through a single pin called ctl when the ce pin is high. the output v com voltage is increased with a mid (v dd /2) to high transition (0.8*v dd ) on the ctl pin. the output v com voltage is decreased with a mid (v dd /2) to low transition (0.3*v dd ) on the ctl pin (see figure 8). once the minimum or maximum value is reached on the 128 steps, the device will not overflow or underflow beyond that minimum or maximum value. programming of the non-volatile memory occurs when the ctl pin exceeds 4.9v. the ctl signal needs to remain above 4.9v for more than 200s. the level and timing needed to program the non-volatile memory is given in figure 2. it then takes a maximum of 100ms for the programming to be completed inside the device. when the part is programmed, the counter setting is loaded into the non-volatile memory. this value will be loaded from the non-volatile memory during initial power-up or when the ce pin is pulled low. once the programming is completed, it is recommended that the user float the ctl pin. the ctl pin is internally tied to a resistor network connected to ground. if left floating, the voltage at the ctl pin will equal v dd /2. under these conditions, no additional pulses will be seen by the up/down counter via the ctl pin. to prevent further programming, ground the ce pin. ctl should have a noise filter to reduce bouncing or noise on the input that could cause unwanted counting when the ce pin is high. the board should have an additional esd protection circuit, with a series 1k resistor and a shunt 0.01f capacitor connected on the ctl pin, (see figure 3). to avoid unintentional adjustmen t, the ISL45042 guarantees to reject ctl pulses shorter than 20s. during initial power-up (only), to avoid the possibility of a false pulse (since the internal comparators come up in an unknown state), the very first ctl pulse is ignored. see figure 8 for the timing information. ce pin to adjust the output voltage, the ce pin must be pulled high (vdd). the ce pin has an internal pull-down resistor to prevent unwanted reprogra mming of the eeprom. to minimize current consumption, t he impedance of this resistor is high: 400k to 5m (see r internal in figure 7). transitions of the ce pin are recommended to be less than 10s. replacing existing mechanical potentiometer circuits figure 4 shows the common adjustment mechanical circuits and equivalent replacement with the ISL45042. r set figure 1. vcom adjustment in an lcd panel ISL45042 set out avdd r 1 r 2 avdd i sink vcom single pixel ctl ce in lcd panel red green blue + - column driver ctl voltage time 4.9v ctl pt figure 2. eeprom programming >200s ISL45042
6 fn6072.9 april 13, 2011 expected output voltage the ISL45042 provides an output sink current, which lowers the voltage on the external voltage divider (v com output voltage). equations 1 and 2 can be used to calculate the output current (i out ) and output voltage (v out ) values. (where ?setting? is an integer between 1 and 128.) table 1 gives the calculated value of v out for resistors values of: r set = 24.9k , r 1 = 200k , r 2 = 243k , and av dd = 10v. r set resistor the external r set resistor sets the full- scale sink current that determines the lowest voltage of the external voltage divider r 1 and r 2 (see figure 1). the voltage difference between the v out pin and i set pin (see figure 5) has to be greater than 1.75v. this will keep the output mo s transistor in the saturation region. expected current settin gs and 7-bit accuracy occurs when the output mos transistor is operating in the saturation region. figure 5 shows the internal connection for the output mos transistor. the value of the av dd supply sets the voltage at the source of the output transistor. this voltage is equal to (setting/128) x (av dd /20). the i set current is therefore equal to (setting/128) x (av dd /20 x r set ). the value of the drain voltage is found using equation 2. the values of r 1 and r 2 in equation 2, should be determined (setting equal to 128) so the minimum value of v out is greater than 1.75v + av dd /20. table 1. calculated vcom output voltages setting value v out 1 5.468 10 5.313 20 5.141 30 4.969 40 4.797 50 4.625 60 4.453 70 4.281 80 4.109 i out setting 128 -------------------- - x av dd 20 r set () --------------------------- = v out r 2 r 1 r 2 + -------------------- - ?? ?? ?? av dd 1 setting 128 -------------------- - x r 1 20 r set () --------------------------- ? ?? ?? ?? = (eq. 1) (eq. 2) figure 3. external esd protection on ctl pin ISL45042 ctl 0.01f 1k - + r a r b r c r set - + ISL45042 set out avdd r 1 r 2 avdd vcom vcom avdd r 1 = r a r 2 = r b + r c r set = (r a (r b + rc)) / 20r b figure 4. example of the replacement for the mechanical potentiometer circuit using the ISL45042 90 3.936 100 3.764 110 3.592 128 3.282 table 1. calculated vcom output voltages setting value v out figure 5. output connection circuit example av dd = 15v rset vout pin r1 r2 avdd vsat 0.5v iset pin setting 128 ---------------------------- x av dd 20 ----------------- - ISL45042
7 fn6072.9 april 13, 2011 power supply sequence the recommended power supply sequencing is shown in figure 6. when applying power, vdd should be applied before or at the same time as avdd. the minimum time for t vs is 0s. when removing power, the sequence of vdd and avdd is not important. do not remove vdd or avdd within 100ms of the start of the eeprom programming cycle. removing power before th e eeprom programming cycle is completed may result in co rrupted data in the eeprom. verifying the programmed value the following sequence can be used to verify the programmed value without having to sequence the v dd supply. to verify the programmed value, follow the following steps. the ISL45042 will read memory contents and be set to that value when the ce pin is grounded. 1. power-up the ISL45042. 2. ce pin = v dd. 3. change counter value with ctl pin to desired value. 4. ctl = more than 4.9v and 200ms. counter value programmed. 5. change the counter value with ctl pin to a different value. 6. ce pin = ground. 7. check that the output value is the one programmed in step 4. generating vdd and ce supply from a larger voltage source the ce pin has an internal pull-down resistor (see r internal in figure 7). the impedance of this resistor is 400k to 5m . if your design is using a resistor divider network to generate the 3.3v supply (for both v dd and ce to enable programming) from a larger voltage source, the 400k (worst case) resistor need s to be taken into account as a parallel resistance when the ce pin is connected to this source. another design concern is to be able to provide enough supply current during programming. the ISL45042 draws about 2ma during this process. recommended resistor values are shown in figure 7. this design will result in an additional 0.83ma quiescent current flowing through resistors r a and r b . figure 6. power supply sequence v dd a vdd t vs figure 7. application generating vdd and vce voltages v cc = 5v schmitt trigger ce logic r internal = 400k to 5m r a r b 2k 4k ISL45042 ce vce ISL45042
8 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6072.9 april 13, 2011 ISL45042 truth table the ISL45042 truth table is shown in table 2. for proper operation the ce should be disabled (pulled low) before powering the device down to assure that the glitches and transients will not cause unwanted eeprom overwriting. . table 2. truth table input output ctl ce vdd out icc memory mid to hi hi vdd increment normal x mid to lo hi vdd decrement normal x x lo vdd no change increased read >4.9v hi vdd no change increased program ctl v dd /2 ctl low ctl high ce 78 79 7a 7b 7a undef. counter output ctl ilmpw ctl mtc ctl ihrpw ctl ilrpw figure 8. ISL45042 timing diagram vcom ce st ignores 1st pulse after programming stop programming after power is 1st applied, the very 1st ctl pulse is ignored the timing diagram above sh ows post power-up timing. note: start programming start programming ctl ihmpw ISL45042
9 fn6072.9 april 13, 2011 ISL45042 package outline drawing l8.3x3a 8 lead thin dual flat no-lead plastic package rev 4, 2/10 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.20mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0 . 2 ref 0 . 05 max. 0 . 02 nom. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 6x 0.65 1.50 0.10 8 1 8x 0.30 0.10 6 0.75 0.05 see detail "x" 0.08 0.10 c c c ( 2.90 ) (1.50) ( 8 x 0.30) ( 8x 0.50) ( 2.30) ( 1.95) 2.30 0.10 0.10 8x 0.30 0.05 a mc b 4 2x 1.950 (6x 0.65) index area pin 1 compliant to jedec mo-229 weec-2 except for the foot length. 7.
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